HDLs/HVLs : |
Verilog, VHDL, SystemVerilog, SystemVerilog Assertions, OVA, Vera
|
HDL Simulators : |
VCS, NCVerilog, ModelSim,QuestaSim |
Tools Used : |
DesignCompiler, PrimeTime, DVE, CoverageMetrics, SignalScan, UnderTow, VirSim, VMC, Hspice, TopProtect, NOHAU incircuit Emulator, HP Logic Analyzer, CRM,Xilinx-ISE, XPS, Chipscope-Pro, Timing Analyzer, XPower, SpyGlass, 0-in CDC, Synopsys Design Compiler, UnderTow, Cadence Virtuoso (Schematic, Layout), SpectreSpice, Syntest TurboBIST,
|
FPGAs: |
Virtex-2P, Virtex-4, Virtex-5, Virtex6, Spartan3, Spartan6
families. |
FPGA Boards: h |
Xilinx ML605, SP605, SP601, ML300, ML403, ML501, ML505,
ML601, Memec Spartan3, Virtex2p.
|
Bus Standards: |
PLB, AXI4, AXI4Lite, AXI4Streaming, AXI3, AHB, APB, OPB, OCP.
|
Hardware debugging tools : |
Logic Analyzer, Xilinx Chipscope |
Embedded Processors : |
IBM PPC 405, IBM PPC 440, MicroBlaze, ARM Cortex A9.
Revision Systems : RCS, XCS, Perforce.
|
Scripting Languages : |
PERL, AWK, C-Shell |
Assembly Languages : |
Intel 80C51 family, Philips eXtended Architecture 51,
Motorola 68HC11
|
Software Packages: |
MicrosoftOffice, MSVisio, Adobe Frame Maker,
Adobe Illustrator and OrCAD.
|
