Design and Development of 5-Stage Processor
16-bit 5 stage pipeline processor is designed and developed in this project. The processor is based on Harvard Architecture which consists of separate Program Memory and Data Memory. The RISC pipeline is broken into five stages; Instruction Fetch, Instruction Decode, Execute, Memory Access, and Register Write Back. To improve the frequency, pipelining is added with a set of flip flops between each stage. The Instruction Set Architecture consists of all of logical and arithmetic operations around 20 different types.
Design and Development of Dynamic scheduling Processor
This project describes scoreboard architecture implementation of a 5-stage pipelined processor, which dynamically schedules the instructions. In dynamic scheduling, the hardware rearranges the instruction execution to reduce stall cycles. The instructions are issued in order but executed out of order, and completed out of order. The fetched instruction is stored in pipe registers at each clock cycle. An instruction will not be issued if a WAW or Structural Hazard exists.
Design and Development of Configurable Arbiter
The effectiveness of any system to resolve priority across multiple requests resides in its ability to grant assignment effectively. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfer. The purpose of this project is to design and develop configurable arbiter where the number of requests can be configurable from 2 to 16. The project also involves developing the configurable arbitration algorithm, such as highest priority or round robin.
Design and Development of ALU using Vedic multiplication & Vedic division
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in designing an efficient ALU. The speed of ALU depends greatly on the speed of multiplier and divider. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on Sutras. Urdhva Triyagbhyam-Vedic method for multiplication is used and Paravartya method- Vedic Division is used to increase the speed of the ALU.
Design and Development of UART Controller using Synchronous FIFO (First In First Out)
Serial data communication is used to efficiently send data over long distances where channel costs are reduced. This project involves developing a Universal Asynchronous Receiver/Transmitter (UART) controller which transmits/receives data stored in a FIFO. The FIFO can store up to 16 characters. The design consists different transmit and receive FIFOs. Different baud rates are supported by using a configurable baud counter. FIFO Full & FIFO Empty conditions are generated and checked by the interface that writes and reads the data from UART.
Design and Development I2C Core using Synchronous FIFO:
I2C is a synchronous protocol which is used for data transfers between Integrated Circuits. It is used in systems, which has more than one IC and it wants to communicate to others. The aim of this project is to design I2C Core which transmits the data from the synchronous FIFO. The data received is also saved in FIFO. I2C master and slave operations are supported. The depth of the FIFO is 16. The design consists separate transmit and receive FIFOs.
Design and Development of Configurable Multichannel Interrupt Controller
Flexibility of interrupt controller is more and more concerned with the development of System-on-Chip(SoC). In this project, a configurable multichannel interrupt controller is developed using Verilog. Interrupt priority is configurable by processor by accessing registers through AXI (Advanced eXtensible Interface) bus. Combination interrupt is also realized for one Interrupt Service Routing (ISR) to service multiple interrupts at a time. Up to 60 interrupt inputs and 12 interrupt channels are supported in this design.
Design and Implementation of Digital Watch
Almost every SOC uses a timer/counter to count the real time. This project involves in developing the Digital watch using multiple counters. The digital watch has free running mode showing H:M:S and also setting mode, using set switch where you can selectively change(initialize) the values of H, M ad S to a known value before jumping into free running mode.
Design and Implementaton of 4x4 Router (switch)
Router is a switch which routes or connects four input channels or data streams of 8 bit each to either of four 8bit output channels. Connection details are part of the data stream itself and no separate address lines are provided. The challenge in this project is to extract destination address of the connection and connect the current input to this destination output, provided it is free and not already serving other input. A simple priority logic is adopted to resolve ambiguity.
Design and Implementation of Nikhilam Sutra (Vedic multiplication)
Nikhilam sutra is ancient vedic multiplication algorithm which circumvents the need of large multipliers by reducing the multiplication of large numbers to that of smaller numbers. This reduces the propagation delay associated with the conventional large multipliers considerably. The project involves in developing and implementing of Nikhilam sutra using Verilog.