16-bit 5 stage pipeline processor is designed and developed in this project. The processor is based on Harvard Architecture which consists of separate Program Memory and Data Memory. The RISC pipeline is broken into five stages; Instruction Fetch, Instruction Decode, Execute, Memory Access, and Register Write Back. To improve the frequency, pipelining is added with a set of flip flops between each stage. The Instruction Set Architecture consists of all of logical and arithmetic operations around 20 different types