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Training on Advanced Digital Design using Verilog @ LUCID VLSI

Training Summary:

·         In class teaching – Twelve 2 Hour  and Twelve 3 Hour Sessions

·         A Total of  (60 Hours)

·         Labs – (No Separate Labs. They are part of the Teaching)

Timings:

·         Saturday: 5pm to 7pm.

·         Sunday: 9am to 12pm

Training Goals:

• Understand Verilog basics, terminology, how it is used for Digital Design
• How to write RTL using Verilog
• Usage of Tools – ModelSim
• Simulation and Debugging of digital circuits – Common issues – How to solve them
• How to write Test benches and Self checking test cases
• Knowing advanced Verilog constructs

1. Introduction to HDL  - 1 Sessions  
• Why Use HDL, Features of HDL, Structural Coding
• BottomUp and TopDown Design Flows
• Simple and Complete example
• Combinatorial Circuit Design and Coding (Both DUT and TB)
2. RTL Coding - 2 Sessions 
• For Sequential circuits.
• Arithmetic, Logic, Equality, Relational, Bitwise, Reduction
3. State Machines - 2 Sessions 
• Mealy/Moore State machines
4. Advanced Verilog Constructs - 4 Sessions
• Conditional compilation
• Blocking and Non-blocking,
• Intra and Inter delays
• Delay modeling (specify blocks)

Assignments/Examples:

1. Coding for Combinatorial circuits. - 8 Sessions
• Building functional blocks 

(Muxes, Comparators and Adders) 

• Verilog Coding for combinatorial circuits like, HA, FA, PriorityEncoder etc
• Verilog Constructs like, “assign”, “initial”
1. Coding for Sequential Circuits - 8 Sessions 

• DFF, Counters,  Clock Generators, etc.
• Verilog Constructs “always”, 
• TestBench Constructs like “repeat”,

3. State Machine  - 8 Sessions

• Arbiter,
• FIFO,
•   Coding DUT and Testbench

4          TestBenches- 6 Sessions 

a.       More Emphasis on TestPlan,

b.      Creating SelfChecking TestBenches

c.       Regressions

d.      Debugging Functionality mistakes

e.       Gate Level Simulation

1)      PLI , VPI

2)      SDF, GateLevel Simulation